Planarity verification system for integrated circuit test probes

ABSTRACT

A planarity verification system for proper positioning of testing probes comprises a plurality of electrical leads configured for connection to testing probes, an indicator electrically coupled to each of the leads, and a power source. One of the power source terminals is electrically coupled to the leads through the indicators and the other terminal is electrically coupled to a metalized surface such as a wafer to bias the surface. Each electrical lead forms part of a completed current path between the power source terminals when a testing probe contacts a biased surface and directs current through an associated indicator to provide an indication.

FIELD OF THE INVENTION

This invention relates generally to the testing and probing ofintegrated circuits formed on a semiconductor substrate and, morespecifically, to a system for verifying the planarity of test probes andtest equipment used for such testing.

BACKGROUND OF THE INVENTION

During the formation of integrated circuits (IC's) on the surface of asemiconductor substrate or wafer, the individual circuits or groups ofcircuits must be tested to determine that they were fabricated correctlyand are functioning properly. Such testing is usually done uponcompletion of the wafer processing to determine if the wafer is suitablefor being packaged into individual IC chips. Alternatively, the IC'smight be tested at various stages during their processing to determineif future processing is desirable for a particular wafer or set ofwafers, or whether the wafer or wafers should be discarded.

The testing of IC's on a wafer is done by using a probing machine orprober. The prober has a number of finely-constructed, elongatedelectrical probes which contact the surface of the wafer to makeelectrical contact with individual IC's thereon. The probes areconnected to diagnostic equipment which is used to verify theoperational characteristics of an IC, such as its resistancecharacteristics and its signal handling capabilities, for example.

Integrated circuit probers are commercially available, and one suchsuitable prober is available from KLA Instruments Corporation of SanJose, Calif. under Model No. KLA-1007. Probers usually have multiple,elongated test probes mounted next to each other on a planar probe card.The elongated probes extend downwardly from the probe card at variouspositions on the card. The probe card is a printed circuit board havingconductive paths that are connected to the individual probes forelectrically coupling the probes to the diagnostic equipment. The probecard, in turn, is mounted to a planar probe card mount or load boardthat is made of a suitable polymer such as glass epoxy laminate. Theplanar probe card and card mount form a probe card assembly. Theindividual elongated test probes, which may be, for example, tungsten ora beryllium/copper alloy, are connected through the probe card assemblyto test leads on the probe card mount. The test leads provide a lowresistance or "zero resistance" path to the probes for electricallyconnecting them to the diagnostic equipment.

In a prober, the planar probe card assembly is positioned opposite to(usually above) and parallel to the planar surface of the semiconductorwafer to be probed and tested. The wafer is supported below the assemblyand probes by a suitable wafer chuck of the prober. For probingpurposes, the chuck moves or translates vertically toward and away fromthe probe card assembly to position the wafer and IC's thereon againstthe ends of the test probes.

Ideally, the planar probe card assembly is parallel to the wafer surfaceand chuck and the probe ends all lie in a single plane which is alsoparallel to the plane of the wafer surface to be tested. In that way,when the chuck is moved toward the probe card assembly, the test probeends contact the wafer surface evenly and at the same time and in theproper positions around the wafer. Usually the wafer chuck is movedslightly past the chuck position of initial probe contact with the waferto ensure a good electrical contact between the probes and the ICs beingtested. However, when the test probes are unevenly positioned and arenot planar in a plane which is parallel with the plane of the wafersurface, damage to both the probes and the wafer may occur, because theends of the test probes do not contact the wafer surface evenly asdesired.

It will be understood by a person of ordinary skill in the art, thatuneven probe positioning and uneven probe end contact on the wafersurface may be caused by a number of factors. For example, tilting ofthe planar probe card assembly and probes, or tilting of the wafersurface, each with respect to the other parallel component, will causeuneven probe end contact. Uneven contact is also caused by probe endswhich are not properly positioned on the probe card assembly and arenon-planar and/or non-parallel with respect to the plane of the wafersurface. More specifically, uneven contact exists when the probe endsare properly positioned on the probe card assembly, but the probe cardassembly plane is not parallel to the wafer surface plane. Conversely,uneven contact also exists when the probe card assembly plane isparallel to the wafer surface plane, but the individual probe ends arenot planar, and in a plane parallel with respect to the wafer surfaceplane. Both conditions will be referred to herein as non-planar probes,wherein planarity of the probes is desired. Planar probes will have endsall within a single plane, and that plane will be generally parallel tothe wafer surface plane.

If the probes are non-planar with respect to the plane of the wafersurface, one or more of the probes will contact the wafer surface beforethe other probes. Uneven surface contact causes uneven wear of theprobes at their ends and early replacement of certain probes on theboard is then required. Probe replacement is an expensive andtime-consuming endeavor. If the wafer chuck is moved only until certainof the probes first make contact, then other of the probes, which arenot in the plane of the contacting probe, will not make solid electricalcontact with the wafer. This prevents accurate testing of the wafer ICs.

Damage to the wafer is also caused by uneven probe contact. The unevencontact of the probes causes certain of the probes to contact the waferbefore the other probes, as mentioned above. To compensate for theskewed or uneven probe contact, the chuck is moved further in thedirection of the probe card assembly. While a certain amount of "overtravel" of the chuck is used to ensure proper probe contact, too muchover travel causes the ends of the probes which contacted earliest toslide out of their proper position on the wafer surface. The probe endsthus scratch the surface of the wafer as they slide, causing damage tothe ICs formed at the surface. Even if no physical damage occurs,movement of the probe end from the desired position prevents accuratetesting of the ICs.

Still further, uneven contact of the probes creates uneven stress on theprobes. The probes are formed to be resilient under certain stresses;however, overstressing will cause the probes to break. The breakage willnot only require replacement of the particular probe, but may damage thewafer as well.

Various prior art methods have been used for achieving parallelorientation and planarity between the individual probe ends and thewafer surface. However, those methods have proven generallyunsatisfactory. Once such method is to imprecisely visually estimate theplanarity and parallel orientation of the probe ends by variations inthe size of the marks left on the wafer surface. Such a task isimprecise and tedious. Furthermore, the difficulty of estimating theplanarity in such a way is further exacerbated by the small scale of theICs. Slight variations of the probe ends from the desired plane andparallel orientation may be sufficient to cause damage to the IC beforeit is detectable in such fashion.

Another method is to make planarity measurements of the probe card mountin the wafer prober without the probe card attached thereto. Suchplanarity measurements are very time-consuming and will not guaranteethat planarity and parallel orientation of the probes will be maintainedupon mounting the probe card.

Furthermore, even when non-planarity of the probes is detected, it isstill difficult to determine how the probes or probe card assemblyshould be adjusted for proper probe contact.

Therefore, it is an objective of the present invention to ensureplanarity and parallel orientation of wafer test probes with respect tothe surface of a wafer.

It is another objective of the present invention to provide even contactbetween the ends of the test probes and the wafer surface during testingprocedures.

It is still another objective of the invention to provide an indicationof the planarity or non-planarity of test probes with respect to a wafersurface.

It is another objective of the invention to prevent probe damage to theintegrated circuits of a wafer being tested.

It is still another objective of the invention to verify the planarityand parallel orientation of the test probe ends in a simple andefficient manner.

SUMMARY OF THE INVENTION

The present invention addresses the above objectives by providing anindication of the position of each probe with respect to the planarwafer surface as the wafer is translated into contact with the testingprobes. More specifically, each probe is coupled to an individualindicator which provides a visual indication of when the probe contactsthe wafer surface.

The planarity verification system of the present invention includes aplurality of electrical leads, preferably including microclips, whichare configured for connection to testing probes. The microclips arephysically clipped onto terminals on the probe card mount which areconnected through low resistance current paths to the testing probes. Alead is associated with each probe. A power source, preferably abattery, has one terminal electrically coupled to the leads and theother terminal electrically coupled to the wafer or other metalizedsurface to be analyzed for biasing the wafer or surface. An indicator iselectrically coupled to each of said leads between the battery terminaland the lead. Therefore, each probe has an associated indicator. Theindicator, which is preferably an LED, provides visual indication whenelectrical current flows therethrough, and a current limiting resistorassociated with each LED ensures the proper current levels.

The testing probes, associated electrical leads, associated indicators,and the biased wafer provide a current path between the terminals of thebattery. The wafer is translated on a moveable wafer chuck toward thetesting probes to contact one or more of the testing probes. Whencontact is made between a testing probe and the biased wafer, a currentpath associated with that testing probe is completed and electricalcurrent flows through the associated probe LED, illuminating the LED. Inthat way, a visual indication is provided when each probe contacts thewafer.

Preferably, the moveable wafer chuck is coupled to a measuring devicewhich is capable of measuring the translation of the wafer chuck andwafer in fine increments, such as micron increments. The distance ofwafer translation which is necessary to produce contact between each ofthe probes is measured. The difference between the distances measuredfor the adjacent testing probes provides an indication of the planarity,or lack of planarity, of the testing probes with respect to the planarsurface of the wafer. For example, if all probes on one side of theprobe card contact the wafer at the same distance measurement, but theprobes on the other side of the probe card contact the wafer at adifferent distance, then the inventive system provides indication thatthe probe card assembly or wafer is tilted with respect to the otherelement. Alternatively, if various probes contact the wafer at variousdifferent measured distances, the inventive system provides anindication that the probes will require more complicated adjustmentrather than simple tilting of the probe card assembly or the wafer.

A commercially available 9-Volt battery is suitable for use with theinventive system, and the current limiting resistors are connected inthe current path with the LEDs for limiting the drain on the batterywhen the probes make contact with the wafer, thereby providing longerbattery life. An ON/OFF switch is also coupled in line for selectivelyenabling or disabling the inventive system.

The present invention provides a system for verifying the planarity ofthe testing probes, including their parallel orientation with respect tothe surface of the wafer. After various measurements are taken regardingthe positions of the probes, the probes can be adjusted, eitherindividually or through movement of the probe card or metal wafer toprovide even contact between the ends of the test probes and the wafersurface. The inventive system is relatively inexpensive and simple touse and the LEDs provide a visual indication of the orientation andplanarity of the test probes and associated testing equipment, thusproviding proper testing procedures and preventing probe damage anddamage to the integrated circuits on the wafer being tested.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments of the invention and,together with a general description of the invention given below, serveto explain the principles of the invention.

FIG. 1 is a side schematic view of a wafer prober utilizing theplanarity verification system of the present invention.

FIG. 2 is a circuit schematic of the planarity verification circuit ofthe present invention schematically illustrating the probes and biasedwafer as portions of a switch.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a side view of one embodiment of the planarity verificationsystem of the present invention. FIG. 2 provides a schematicillustration of the electrical operation of the various components ofthe inventive system.

Turning to FIG. 1, system 10 is utilized as part of a wafer probingsystem or prober 13 which is utilized to test and analyze the integratedcircuits of a semiconductor wafer. Probers are commercially availableand one such suitable prober is available from KLA InstrumentsCorporation of San Jose, Calif., under Model No. KLA-1007. The prober 12essentially includes a wafer supporting chuck 12 which supports asemiconductor wafer 14 on an upper surface 16 thereof. The wafer 14, forthe purposes of the invention, is preferably metalized. That is, it hasa metal layer on the upper surface 15 or at least metalized layers onportions of surface 15. The metal layer on the wafer 14 is to ensuresuitable electrical conductivity of the wafer when the invention isused. Wafer chuck 12 is vertically translatable in the direction ofreference arrow 18 for moving wafer 14 vertically toward and away fromtesting probes 20 for analyzing the integrated circuits on wafer 14.Chuck 12 is part of the overall prober system.

The testing probes 20 are elongated, finely-constructed metal elementsformed of tungsten or a beryllium/copper alloy. The probes have freeends 22 which contact the upper surface 15 of wafer 14 when the wafer 14is moved against the probes 20. The other ends of the probes aremounted, such as by soldering, to a probe card 24. The probe card is aprinted circuit board, preferably rectangular, which includeslow-resistance, conductive paths 32 coupled to the various probes 20. Ina preferred embodiment, probes are positioned at the four corners of therectangular probe card 24.

The probe card 24 is mounted to an appropriate probe card mount 26. Theprobe card mount, also referred to as a load board, is formed of asuitable polymer, such as glass epoxy laminate. The probe card 24 issecured to card mount 26 by a plurality of securement pins 28. The probecard mount 26 includes a plurality of metal terminals 30 which areelectrically coupled to the probes 20 through the low-resistance or"zero-resistance" paths 32. The terminals 30 may be any suitablyconductive structure such as an excess amount of solder or an upstandingpin.

In accordance with the principles of the present invention, a pluralityof electrical leads 36, including clipping devices, such as microclips38, are coupled to the terminals 30 and thus are electrically coupled tothe testing probes 20. Suitable microclip structures are available fromRadio Shack.

Coupled to each lead 36 is an indicator which is operable for providinga humanly-perceptible indication when electrical current flows throughthe indicator. In a preferred embodiment of the invention, asillustrated in FIG. 1, one such suitable indicator is a light device,such as an LED 40, for providing a visual indication to an operatorusing the invention. The leads 36 and LEDs 40 are coupled to oneterminal 41 of a power source, such as a battery. Another terminal 43 ofthe power source is electrically coupled to wafer 14 through the waferchuck 12. As illustrated in FIG. 1, line 44 indicates the electricalcoupling between terminal 43 and wafer 14. In that way, wafer 14, andparticularly the metalized surface 15 of the wafer, is biased by powersource 42. In a preferred embodiment of the invention, power source 42is a battery, such as a commercially available 9-Volt battery, having apositive terminal 41 coupled to one side of the LEDs 40, and a negativeterminal 43 coupled to wafer 14 to negatively bias the wafer and wafersurface 15.

The probes 20, clips 38 and leads 36, LEDs 40, and the wafer 14 on line44 form a current path between the terminals 41,43 of battery 42. Eachindicator is coupled between the leads 36 and clips 38 and the terminal41. Current limiting resistors R1, R2, R3, R4 (R1-R4) are coupledbetween the LEDs 40 and terminal 41 for limiting the current travelingthrough the current path for proper operation of the LEDs. Referring tothe bottom portion of FIG. 1, it will be seen that when wafer chuck 12has been vertically translated to move the wafer 14 below the ends 22 ofprobes 20, the current path is broken to create an open circuit. In sucha position, the probe ends 22 do not contact biased surface 15 of wafer14, and thus no current flows through the LEDs 40 which are notilluminated. However, to determine the planarity of the probes 20, andspecifically the probe ends 22 in accordance with the principles of thepresent invention, wafer chuck 12 is translated upwardly to move wafer14 into contact with one or more of the probe ends 22. When one of theprobe ends contacts wafer 14, a circuit path is completed to provide acomplete current path between the battery terminals 41, 43. In that way,LEDs 40 associated with the contacting probes are illuminated. Forproper electrical conduction, wafer 14 will generally be a metal coatedwafer, or a wafer which is highly doped with a metal to provide a verylow effective resistance to the current flow.

In that way, the inventive system 10 may be utilized to determinepositioning of the probes 20 with respect to each other and also withrespect to the planar upper surface 15 of wafer 14. As utilized herein,the term planarity verification is used to indicate that the probes 20,and specifically the ends of the probes 22, are all within a singleplane, which plane is oriented parallel to the planar upper surface 15of the wafer 14. Therefore, as mentioned above, the term "planarity"used to describe the probes 20 and probe ends 22 refers not only to allthe ends being within a single plane, but also the characteristic thatthe plane is oriented parallel to the plane of wafer surface 15. Whenthe ends of the testing probes 22 are planar, each of the probe ends 22will contact wafer surface 15 at the same time when chuck 12 istranslated vertically toward the probe card assembly, including theprobe card 24 and the probe card mount 26. Planarity of the probes isthe desired condition for proper utilization of the probes to testintegrated circuits on the wafer upper surface 15. As mentioned above,if the probes are not planar, they will wear unevenly or break.Furthermore, if one or more probes are not planar, proper contact of allthe probes will be difficult to achieve and wafer damage may alsoresult.

The inventive system 10 provides a visual indication of the planarity ornon-planarity of the various testing probes 20 and thus allows anoperator to verify planarity or to determine how the probe card 24 orindividual probes 20 should be moved to achieve planarity so that whenwafer 14 is moved against the probes 20, all the probe ends 22 contactthe wafer evenly and generally at the same time.

As discussed above, lack of planarity, as indicated by the system 10 ofthe invention, might be caused by a number of factors. For example, allthe probes may be properly positioned on probe card 24; however, theprobe card may be tilted with respect to the wafer surface 15.Alternatively, the probe card 24 and wafer surface 15 may be parallel,but one or more of the probes might be positioned such that its end 22is out of the proper plane and thus will contact the wafer surface 15before or after the other probes when chuck 12 is translated verticallytoward the probe card assembly. Still further, the probe card 24 andwafer surface 15 may be parallel, and the probe ends 22 may be coplanar.However, the plane of the probe ends 22 might be tilted with respect towafer surface 15. As a result of any one of the above scenarios, whenthe probes 20 are not planar, the LEDs 40 will be illuminated atdifferent times corresponding to different heights of the wafer chuck 12and wafer 14 as the chuck is translated. By monitoring the LEDs, anoperator moving the chuck can verify which probe or probes are out ofposition. Accordingly, adjustments to the probe card assembly and/or theindividual probes 20 may be made to achieve planarity. Adjustment of thewafer chuck 12 and the wafer 14 might also be made. However, adjustmentis substantially more difficult than adjusting the probe card assemblyand probes.

In a preferred embodiment of the invention, the translatable chuck 12 ofthe prober includes a distance gauge for measuring the translationdistance in the direction of arrow 18. In the art, the vertical motionof the wafer chuck and wafer in the direction of arrow 18 is generallyreferred to as the Z-motion of the wafer, corresponding to aZ-coordinate axis, wherein the plane defined by the X and Y Coordinateaxes is the plane of wafer surface 15. Distance gauge 50, in oneembodiment of the invention, is a micrometer, which measures theZ-motion in microns (μm).

While there may be various reasons for lack of planarity with respect tothe ends of the probes 22 and their uneven contact with wafer surface15, a predominant reason for the lack of planarity within a prober islack of parallel orientation of the probe card 24 with respect to wafersurface 15 when the probe card is installed within the wafer prober.Accordingly, once the planarity measurements are made utilizing thepresent invention, the probe card will generally be adjusted accordingto well-known principles to achieve planarity and an even contactbetween the probe ends 22 and wafer surface 15.

To measure planarity, wafer chuck 12 is translated vertically until theprobes engage wafer surface 15. The operator analyzes each of theindividual LEDs 40 to determine which LEDs are illuminated, and in whatorder, as the probe ends 22 contact surface 15. If all of the probe ends22 contact surface 15 generally at the same time, the invention willindicate such by simultaneous, or almost simultaneous, illumination ofthe LEDs 40. If one or more of the LEDs lights before the other LEDs,lack of planarity is indicated by the invention. Monitoring the distancegauge, the difference in distance between the first probe to engage andthe last probe to engage is measured, as well as the distance variationsbetween the first and last probes and the other probes of the system.For a probe card which is tilted, the probes on one side of the cardwill contact before the probes on the other side of the card. For othervariations between wafer surface 22 and the ends 22 of the probes,different illumination patterns of LEDs 40 will occur. Once thevariation in planarity is known to an operator using the invention, aperson of ordinary skill in the art will be able to adjust the probecard and/or individual probes until even contact and planarity isachieved. In the preferred embodiment of the invention, severalplanarity readings are made to ensure proper positioning of the probes20 and to verify their position once positioned. While the Figures ofthe application illustrate four probes, it will be readily understoodthat an additional number of probes may be utilized as well, inaccordance with the principles of the present invention for furtherverifying the planarity of the probe card and the ends 22 of the probeswith respect to the wafer surface 15.

FIG. 2 illustrates an electrical schematic of the effective circuitprovided by the inventive system 10 as utilized with the prober. Theelectrical leads 36, clips 38, probes 20, and wafer 14 effectively forma plurality of electrical "switches." In an open condition, or Position1, as illustrated in FIG. 2, the probes are suspended above wafer 14 andthe various circuits, or current paths, are open. In that way, nocurrent flows through the LEDs 40 to illuminate the LEDs and to providea visual indication that the probe 20 is contacting wafer surface 15. InPosition 2, as illustrated in FIG. 2, wafer chuck 12 is translated tomove wafer surface 15 into contact with the probe ends 22 to completevarious of the current paths associated with the LEDs. Each contactingprobe closes the current path, or closes the switch, as indicated inFIG. 2 so that current flows between the battery terminals 41, 43 andthrough the LEDs 40 to illuminate the LEDs.

The main power switch 52 may be utilized in line with the current pathformed by the inventive planarity verification system 10, the waferchuck, and probe card assembly for turning system 10 ON and OFF asappropriate. Switch 52 also prevents premature draining of the battery.

Since test hardware associated with the wafer prober may be damaged bythe biasing provided by battery 42, certain of the test hardware mayneed to be electrically disconnected from the probe card assembly and/orthe wafer chuck to avoid such damage.

In the embodiment of the invention illustrated in the Figures, theplanarity verification system 10 is shown as a separate system which iselectrically coupled to the hardware of a prober. However, in analternative embodiment of the invention, system 10 may be incorporatedinto the probe card assembly as desired.

While the present invention has been illustrated by the description ofthe embodiments thereof, and while the embodiments have been describedin considerable detail, it is not the intention of the applicant torestrict or in any way limit the scope of the appended claims to suchdetail. Additional advantages and modifications will readily appear tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details representative apparatusand method, and illustrative examples shown and described. Accordingly,departures may be made from such details without departure from thespirit or scope of applicant's general inventive concept.

What is claimed is:
 1. A planarity verification system for properpositioning of testing probes used to analyze integrated circuits on awafer, the system comprising:a plurality of electrical leads, each leadconfigured for connection to a testing probe; a light deviceelectrically coupled to each of said leads and operable for beingilluminated and providing an indication when an electric current flowstherethrough; a power source for providing electric current betweenopposing terminals thereof, one of said terminals being electricallycoupled to said leads through the indicators and the other of saidterminals being electrically coupleable to a wafer to be analyzed forbiasing the wafer; each electrical lead forming part of a completedcurrent path between said power source terminals when a testing probeconnected to said lead contacts a biased wafer being analyzed, the leaddirecting current along said current path and through an associatedindicator to provide an indication; whereby the contact of a testingprobe with a wafer is indicated for determining the position of theprobes with respect to the wafer.
 2. The system of claim 1 wherein saidelectrical lead includes a clip operable for physically clipping to aportion of a conductive path connected to a probe.
 3. The system ofclaim 1 further comprising a current limiting resistor coupled betweensaid indicator and said power source terminal coupled to the indicator.4. The system of claim 1 wherein said power source includes a battery.5. A planarity verification system for proper positioning of testingprobes used to analyze integrated circuits of a semiconductor wafer, thesystem comprising:a metalized wafer containing integrated circuits; aplurality of testing probes for contacting said wafer to analyzeintegrated circuits thereon; a light device electrically coupled to eachof said probes and operable being illuminated and for providing anindication when an electric current flows therethrough; a power sourcefor providing electric current between opposing terminals thereof, oneof said terminals being electrically coupled to said probes through theindicators, the other of said terminals being electrically coupled tosaid wafer to bias the wafer; each probe forming part of a completedcurrent path between said power source terminals when the probe contactsthe biased wafer, the current path directing current through anindicator associated with the probe to provide an indication of theprobe contact; whereby the contact of a testing probe with a wafer isindicated for determining the position of the probes with respect to thewafer.
 6. The system of claim 5 wherein each of said testing probesincludes a conductive path, the system further comprising a plurality ofelectrical leads, each lead configured for connection to a testing probethrough said conductive path.
 7. The system of claim 5 furthercomprising a current limiting resistor coupled between said indicatorand said power source terminal coupled to the indicator.
 8. The systemof claim 5 wherein said power source includes a battery.
 9. The systemof claim 5 further comprising a wafer chuck to support the wafer, one ofsaid wafer chuck and said plurality of testing probes being translatablefor providing contact between said probes and said biased wafer.
 10. Thesystem of claim 9 further comprising a gauge for measuring thetranslation of one of said plurality of testing probes and said waferchuck, said gauge providing a measurement of distance translated forcontact between said probes and biased wafer.
 11. A method of verifyingthe planarity of testing probes used to analyze integrated circuits on asemiconductor wafer, the method comprising:positioning a wafer oppositea plurality of testing probes; biasing the testing probes with oneterminal of a power source and biasing the wafer with another terminalof the power source to form a current path between the terminals;electrically coupling a light device to each test probe and in saidcurrent path, the indicator operable for being illuminated and providingan indication when current from said current path flows therethrough;translating one of said wafer and said plurality of test probes toproduce contact between at least one of the probes and the biased waferto complete said current path so that current flows through theassociated indicator to provide an indication of the probe contact;whereby the contact of a testing probe with the wafer is indicated fordetermining the position of the probes with respect to the wafer. 12.The method of claim 11 further comprising limiting the current flowingin said current path.
 13. The method of claim 11 wherein said powersource includes a battery.
 14. The method of claim 11 further comprisingmeasuring the translation of one of said wafer and said plurality oftesting probes to provide a measurement of distance translated toproduce contact between a probe and the wafer.
 15. The method of claim14 further comprising comparing the distance measurement for at leastone of said probes to the distance measurement for another of saidprobes to determine a distance differential between the probes fordetermining the planarity of the probes with respect to the wafer.
 16. Aplanarity verification system for proper positioning of testing probes,the system comprising:a plurality of electrical leads, each leadconfigured for connection to a testing probe; a light deviceelectrically coupled to each of said leads and operable for beingilluminated and providing an indication when an electric current flowstherethrough; a power source for providing electric current betweenopposing terminals thereof, one of said terminals being electricallycoupled to said leads through the indicators and the other of saidterminals being electrically coupleable to a generally planar metalsurface for biasing the metal surface; each electrical lead forming partof a completed current path between said power source terminals when atesting probe connected to said lead contacts the biased surface, thelead directing current along said current path and through an associatedindicator to provide an indication; whereby the contact of a testingprobe with the metal surface is indicated for determining the positionof the probes with respect to the surface.
 17. The system of claim 16wherein said electrical lead includes a clip operable for physicallyclipping to a portion of a conductive path connected to a probe.
 18. Thesystem of claim 16 further comprising a current limiting resistorcoupled between said indicator and said power source terminal coupled tothe indicator.
 19. The system of claim 16 wherein said power sourceincludes a battery.
 20. A method of verifying the planarity of testingprobes, the method comprising:positioning a generally planar metalsurface opposite a plurality of testing probes; biasing the testingprobes with one terminal of a power source and biasing the metal surfacewith another terminal of the power source to form a current path betweenthe terminals; electrically coupling a light device to each test probeand in said current path, the indicator operable for being illuminatedand providing an indication when current from said current path flowstherethrough; translating one of said metal surface and said pluralityof test probes to produce contact between at least one of the probes andthe surface to complete said current path so that current flows throughthe associated indicator to provide an indication of the probe contact;whereby the contact of a testing probe with the surface is indicated fordetermining the position of the probes with respect to the surface. 21.The method of claim 20 further comprising limiting the current flowingin said current path.
 22. The method of claim 20 wherein said powersource includes a battery.
 23. The method of claim 20 further comprisingmeasuring the translation of one of said metal surface and saidplurality of testing probes to provide a measurement of distancetranslated to produce contact between a probe and the surface.
 24. Themethod of claim 23 further comprising comparing the distance measurementfor at least one of said probes to the distance measurement for anotherof said probes to determine a distance differential between the probesfor determining the planarity of the probes with respect to the surface.